The present invention generally relates to a rational frequency divider for generating an integer frequency from a rational frequency.
Processors such as the Pentium and Pentium II from Intel or the K6 from AMD which are frequently used, need a rational frequency (for example, 200/3 MHz=66.{overscore (6)} MHz) for operating the system buses (memories, PCI). Selecting such a frequency results in integral memory cycle times (15 ns at 66.{overscore (6)} MHz). Deviating, for example, from the rational frequency 66.{overscore (6)} MHz to the integer frequency 66.0 or 67.0 MHz is not permissible here since the operation of the processors cannot be guaranteed in such cases.
Other functions such as, for example, the operation of a real-time clock or the calculation of fee data in switching systems, however, require integral frequencies. To achieve an integer frequency, a crystal generator is normally used which generates oscillations of an integer frequency. The disadvantage, however, is that an asynchronous interface is created which is hard to operate.
Furthermore, it is known to divide the rational processor frequency by an integer, more precisely by a natural number (e.g., by 66 or 67) to achieve an integer frequency. The disadvantage of this, however is, that a large tolerance is created to which the real-time clock must be frequently corrected and an additional correction is required for each call charge registration.
From patent U.S. Pat. No. 5,714,896, a frequency divider for generating an integer frequency from a rational frequency is known. The frequency divider contains a memory for storing a first divider constant and a second divider constant. A selection device is used for selecting one of the two divider constants. A first counter is contained in a programmable frequency divider which divides in synchronism with the oscillation of the rational frequency. In addition, the frequency divider contains a counter which is coupled to the selection device and which counts a number of predetermined time intervals in which one of the two divider constants is used. A further counter also is coupled to the selection device and is used for counting the time intervals in which the other divider constant is used. Thus, three counters are used so that the circuit complexity is comparatively high. In addition, a control unit must switch between the counters for the time intervals.
From the article by P. Larsson, xe2x80x9cA wide-Range Programmable High-Speed CMOS Frequency Dividerxe2x80x9d, IEEE Int. Symposium on Circuits and Systems, US, New York, 1995, a frequency divider for generating an integer frequency from a rational frequency is known. The frequency divider contains three counters, one of which is programmable and counts in synchronism with the oscillations of the rational frequency. The programmable divider divides as a function of a divider constant stored in a register. The programmable divider also contains a comparison device and is driven by a control unit which selects one of two divider constants.
From patent application JP 57 138221 A, a switchable frequency divider is known which divides in accordance with a divider constant or in accordance with half the value of the divider constant. The frequency divider contains a counter and a comparison device.
It is, therefore, an object of the present invention to create a rational frequency divider in which the disadvantages described above do not occur, and to provide a corresponding method.
Accordingly, a rational frequency divider for generating an integer frequency from a rational frequency is provided by the present invention which includes: a memory for storing first and second divider constants; a selection device for selecting one of the stored divider constants; a first counter which counts in synchronism with the oscillations at the rational frequency; a comparison device which compares the value of the first counter with the selected divider constant; a second counter which is coupled to the selection device and the comparison device and counts a number of predetermined time intervals; and a pulse generating device for forming the integer frequency by generating a pulse in response to a signal from the comparison device. The device of the present invention provides with little circuit expenditure a rational frequency divider which is suitable for generating an integer frequency from a rational frequency.
According to a preferred embodiment of the present invention, the rational frequency divider is constructed in such a manner that it is suitable for generating an integer frequency from a rational frequency in accordance with the relation       f    g    =            f      0              g              z        n            
where fg is the integer frequency, f0 is the rational frequency, g is a first divider constant, z is a divider constant counter, n is the number of time intervals, and g, z and n are natural numbers. In particular, the memory has areas for storing n-z first and z second divider constants g and g+1, respectively. The selection device is constructed in such a manner that the stored divider constants are, in each case, selected once within one cycle of n time intervals during operation. The first counter is constructed in such a manner that it is reset to the value 1 in response to a signal of the comparison device which indicates the quality of the value of the first counter with the selected divider constant. The second counter is constructed in such a manner that it is incremented by the value 1 and, after reaching the value of n, is reset to 1 in response to a signal of the comparison device which indicates the equality of the value of the first counter with the selected divider constant.
Moreover, the present invention creates a method for generating an integer frequency from a rational frequency which includes the steps of:
a) determining and storing the quantities g, z and n in accordance with the relation             f      g        =                  f        0                    g                  z          n                      ,
xe2x80x83where fg is the integer frequency, f0 is the rational frequency, g is a first divider constant, z is a divider constant counter and n is the number of time intervals and g, z and n are natural numbers, and the quantity g+1 represents a second divider constant; b) initializing a first counter which counts in synchronism with the oscillations of the rational frequency, and a second counter which counts the time intervals, to the value 1; c) selecting the first or second divider constant; d) counting the first counter in synchronism with the oscillations of the rational frequency; e) detecting the equality of the value of the first counter and of the selected divider constant; f) generating a pulse on the detection of the equality of the value of the first counter and of the selected divider constant for forming the integer frequency; g) resetting the first counter to the value 1; g) incrementing the second counter by 1; I repeating steps c) to h), the first divider constant being selected (n-z) times, and the second divider constant being selected z times, during a cycle of n time intervals; and k) resetting the second counter to the value 1 after the second counter has reached the value of n and steps c) to g) have been performed n times. The oscillation generated in accordance with the method the present invention has the precise predetermined integer frequency in each case immediately after the nth time interval.